U.S. Pat. No. 6,080,613 discloses a semiconductor structure comprising a plurality of gate stacks, the gate stacks having thinned sidewall spacers made of silicon oxide.
U.S. Pat. No. 5,439,835 discloses the use of a mask for forming sidewall spacers on gate stacks.
U.S. Pat. No. 6,383,863 B1 discloses gate stacks comprising caps made of silicon nitrite.
Although applicable in principle to any desired integrated circuits, the present invention and the problem area on which it is based are explained with regard to integrated DRAM memory circuits in silicon technology.
The memory cells of integrated DRAM memory circuits comprise a bit line contact, a selection transistor and a storage capacitor. The capacitor may be embodied as a trench capacitor or as a stacked capacitor above the gate lines.
The bit line contacts are etched in a self-aligning manner between gate lines arranged in strip-type fashion and are subsequently filled with a conductive material, metal or highly doped polysilicon. In specific designs, a bit line contact is used for two adjacent memory cells which likewise has a space-saving effect.
As memory cell dimensions decrease, the lateral opening of the bit line contacts also becomes smaller and smaller since the distance between the gate lines decreases. Therefore, considerable efforts have to be made in order to keep the resistance of the bit line contact plug small, which is achieved for example by changing from a polysilicon filling to a suitable metal filling (e.g.) tungsten).
It is also a central problem to find a suitable etching for the bit line contact, that is to say an etching of doped SiO2 selectively with respect to the silicon nitride covering the gate lines, the etching ensuring an opening of the bit line contact hole without damaging the gate lines or the insulation thereof. This is critical in particular owing to the process and thickness fluctuations occurring in the layers that form or insulate the gate lines.
What are particularly critical are the width of the gate line stacks, the thickness of the side wall spacer and also the thickness of a liner made of silicon nitride that functions as a diffusion barrier in order to avoid impurities of the doped SiO2 in the gate lines.
In the case of the 110 nm technology, by way of example, taking account of these process and thickness fluctuations, a fluctuation range of 45 nm to 75 nm remains for the width of a respective bit line contact.
Considerable efforts have been made heretofore in order, by way of example, to optimize the aforementioned self-aligned contact hole etching of the doped SiO2 for the bit line contacts. A principal difficulty consists in the fact that the lateral dimensions are reduced by the shrink factor but the height of the gate stack is scarcely reduced. This increasingly worsens the so-called aspect ratio (height/width) for the critical contact hole etching.
Nowadays the etching process is realized by a two-stage etching. In the first step, etching is effected as far as possible perpendicularly anisotropically as far as the silicon nitride cap, and, in the second step, etching is effected as far as possible selectively with respect to the silicon nitride cap, in which case the profile of the upper region of the contact hole should as far as possible not be expanded.
Reducing the material thicknesses for the individual constituent parts of the gate line stack likewise requires considerable efforts. By way of example, it is known that even only slightly reducing the thickness of the side wall oxide considerably impairs the leakage current behavior of the selection transistors, with the result that the required retention time of the memory signal in the storage capacitor can no longer be guaranteed.
The problem area on which the present invention is based consists in alleviating the space problem for the bit line contacts.